1. Technical Field
The invention relates generally to microelectronics fabrication, and more particularly, to structures and methods for evaluating the effect of process environment variations across a chip.
2. Background Art
In the microelectronic fabrication industry, there is often a need to evaluate the effect of process environment variations on a chip and, in particular, across a chip. For example, oftentimes data pertaining to electrical properties of threshold voltage (Vt) of field effect transistors (FETs) based on variations in a process is required. More specifically, it may be required to evaluate the variation of PFET and NFET threshold voltage with respect to process environment variations experienced during fabrication. Threshold voltage (Vt) may vary within a chip, for example, due to variations in gate length caused by reactive ion etching (RIE) load variation or photoresist planarization variations. In another example, a pattern density of various material stacks can modulate the rapid thermal anneal (RTA) temperature locally and may cause as much as 100 mV variation in threshold voltage (Vt) within a chip. One approach to this problem is to measure an electrical property of two transistors and then to characterize across chip variation based on those measurements. This approach, however, can require a very large sample size of transistors to provide adequate data for variations over many length scales. For example, the characterization does not enable an evaluation of a direction of the process environment variation on the chip. Currently, there is no mechanism available for accurately determining a magnitude and a direction of the effect of a process environment variation across a chip.